This application is based on Japanese Patent Application Nos. 2000-106991 filed on Apr. 7, 2000, and 2000-398749, filed on Dec. 27, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a lateral MOSFET (LDMOS) in which a source region and a drain region are arrayed in the lateral direction of a semiconductor substrate.
2. Related Arts
A power element has a structure in which several tens thousand to several hundreds thousand small LDMOSs are connected in parallel in general and these LDMOSs are operated at the same time to obtain an output.
However, there has been a problem that when a large current such as ESD (electrostatic discharge) flows through the LDMOSs instantly, the element is destroyed or wires connected to the element melt because the large current does not flow though all of the LDMOSs uniformly, but the large current concentrates on some of the LDMOSs.
Therefore, it has been required to improve a capacity for ESD surge. A high capacity for ESD surge of around 10 kV/mm2 has been required in particular in the field of vehicular application. Although a method of adding external devices such as a capacitor to the outside of the IC chip has been adopted in the past to improve the capacity for ESD surge, such method inevitably increases the cost.
In view of the problem described above, it is an object of the invention to provide a semiconductor device whose capacity for ESD surge can be improved.
In order to achieve the above-mentioned object, the inventors have studied following points.
A non-uniformity of current at the time of ESD surge occurs due to variations of electrode resistance on a chip for example. The non-uniformity of current occurs because of a wire bonding section, that is, a current flowchange based on awire resistance. In concrete, a current carrying through a LDMOS near the wire bonding section flows well because the wire resistance is small. While a current carrying through a LDMOS far from the wire bonding section does not flow well because the wire resistance is large in comparison with the LDMOS near the wire bonding section.
A circuit in which an ESD surge generating circuit 50a shown in FIG. 13 is connected to an LDMOS chip 50b in which three cells of LDMOSs 51a, 51b and 51c are provided, i.e., a circuit in which the three cells of the LDMOSs 51a through 51c are connected to a high voltage generating circuit and resistors 52 and 53 which correspond to the resistance of wires according to a distance from a wire bonding section are disposed among the drain terminals of the respective LDMOSs 51a through 51c. 
When a switch 54 is turned ON, power is supplied from a high voltage power source 55 and a capacitor 56 is charged in the surge generating circuit 50a. Then, when a switch 57 is turned ON after turning OFF the switch 54, an ESD surge current flows through the three cells of the LDMOSs 51a through 51c, respectively. Since an L load 58 is included within the circuit, a large current caused by the ESD surge current flows through the three cells of the LDMOSs 51a through 51c at this time.
Then, when the inventors conducted a simulation analysis with such circuit, drain currents Id1 ID2 and Id3 of the respective MOSFET 51a through 51c and drain voltages Vd1, Vd2 and Vd3 of the respective MOSFET 51a through 51c were represented is as shown in FIG. 14.
As it is apparent from this chart, although the drain current Id1 flowing through the LDMOS 51a directly connected with the power supply line suddenly increases from the start of a concentration of current, the drain currents Id2 and Id3 flowing through the LDMOSs 51b and 51c connected to the power supply line via the resistors 52 and 53 decrease.
It is because a current-voltage characteristics of the LDMOS has a negative resistance. Namely, the current flowing through the LDMOS 51a comes into values on a negative resistance region so that a positive feedback occurs and a drain voltage drops when the concentration of current starts as indicated by the upward arrow in the in FIG. 15, while currents flowing through each of the LDMOSs 51b and 51c does not come into the values on the negative resistance region, thereby dropping the currents flowing through the LDMOSs 51b and 51c with drop of each drain voltage as indicated by a downward arrow in FIG. 15.
The negative resistance occurs when a voltage between a source and a drain decreases although the drain current is still increasing. This voltage drop occurs due to the fact that a width of the depletion layer at a PN junction does not vary although the drain current is still increasing.
That is, although the voltage between the source and the drain corresponds to an integral value of electric field strength between the source and the drain, the voltage between the source and the drain is decreased because the field strength drops when the drain current becomes a large current. As a result, the negative resistance occurs.
The inventors obtained results shown in FIGS. 16A and 16B by simulating changes of a distribution of field strength under two different conditions, i.e., the drain current is 20A and the drain current is 200A. The field strength at a part A-Axe2x80x2 in FIGS. 16A and 16B is shown in FIG. 17. It also can be seen from the result that the voltage between the source and the drain, which corresponds to the integral value (area) of the field strength between the source and the drain, decreases when the drain current increases, thus causing the negative resistance.
As described above, the LDMOS has the negative resistance shown in FIG. 15. As a resistance of the LDMOS 51a is inside of the negative resistance region, a current flowing through the LDMOS 51a increases with a decrease of voltage applied between a source and a drain of the LDMOS 51a. However, resistance between a source region and a drain region in each of the LDMOSs 51b and 51c is outside of the negative resistance region, so that the current applied to each of the LDMOSs 51b and 51c decreases.
Therefore, the ESD surge current concentrates on the LDMOS 51a, thus destroying the element of the LDMOS 51a or melting a wire connected with the LDMOS 51a. 
After all, it is possible to prevent the local concentration of the ESD surge current and to improve the capacity for ESD surge by improving the negative resistance described above. The inventors studied about the improvement of the negative resistance.
The negative resistance occurs while the drain current is still increasing although a width of the depletion layer at a PN junction does not vary as described above. Accordingly, the inventors considered that the negative resistance may be improved by modifying a structure by which the width of the depletion layer formed at the PN junction may is acquired, i.e., by modifying a structure in which the depletion layer hardly extends in the vicinity of the drain region.
Then, as a result of trials and errors, the inventors devised an LDMOS shown in FIG. 18 as the structure satisfying the above conditions.
The LDMOS has a structure in which a drain region is surrounded by an n-type region 6. An impurity concentration in the n-type region 6 is set so that the impurity concentration gradually increases from a semiconductor layer 1 to the drain region 5. In other words, the closer to the drain region 5 centering on the drain region 5, the denser the concentration of n-type impurity concentration in the n-type region 6 becomes.
The inventors conducted a simulation analysis to simulate how the negative resistance changes by changing the impurity concentration in the n-type region 6, or more concretely an impurity concentration in a surface part of the n-type region 6 (hereinafter referred to as a surface concentration).
FIG. 19 shows a result. It is noted that the above-mentioned analysis was carried out by the simulation under a diffusion condition that the surface concentration in the n-type region 6 is changed within a hatched range in FIG. 20. More specifically, the analysis was carried out by changing the surface concentration in the n-type region 6 within a range from a surface concentration which is equal to the case when no n-type region 6 is provided to a surface concentration of approximately 2xc3x971017 cmxe2x88x923 under a diffusion condition that a concentration at the depth of 2 xcexcm from the surface of the substrate turns out to be {fraction (1/10)} of the surface concentration as shown in FIG. 20.
It can be seen from this result that two inflection points 1 and 2 exist in the current-voltage characteristics. It is considered that one of factors for these two inflection points 1 and 2 may be that a parasitic transistor formed by the source region 8, the base region 7 and a drift region (n-type substrate 1) turns ON or that a high electric field region reaches to the drain region 5.
Then, in order to analyze the factor of the two inflection points 1 and 2, the source region 8 of the LDMOS shown in FIG. 18 was eliminated to have a diode structure and a negative resistance of this diode structure was checked out. The result is shown in FIG. 22.
As it is apparent from this result, there is only the inflection point 2 in the diode structure. It can be seen from this result that the inflection point 1 among the two inflection points 1 and 2 was caused by the parasitic transistor.
Then, it can be seen that the inflection point 2 shifts to high values of the current Id with increase of the surface concentration in the n-type region 6. It also can be seen from FIG. 22 that the inflection point 2 occurs by a breakdown of the PN junction at a time when an expansion of the depletion layer is suppressed due to a high concentration of the drain region after reaching the drain region, whereby an electric field becomes strong.
On this account, it is possible to arrange such that a current value, from which a resistance between the source region and the drain region of the LDMOS change into the negative resistance region, increases. In other words, the resistance between the source region and the drain of the LDMOS hardly come into the negative resistance region in the current-voltage characteristics by increasing the surface concentration.
Accordingly, it is possible to prevent the resistance between the drain region and the source region of one or some of the LDMOSs from being in the negative resistance region in low level of the current flowing through the LDMOS and to prevent the large current from locally flowing, thereby improving the capacity for the ESD surge.
Meanwhile, it is considered that the remaining inflection point 2 may occur due to the fact that a high electric field region extends and reaches to the drain region 5. Then, the inventors simulated a distribution of electric field strength to check out how the high electric field region extends by setting the surface concentration in the n-type region 6 at a predetermined value (here, 5xc3x971016 cmxe2x88x923) and by changing the value of drain current. As a result, the result shown in FIG. 23b was obtained. It is noted that a horizontal axis of the distribution of field strength in FIG. 23b corresponds to a lateral direction of the diode structure shown in FIG. 23c. 
As it is apparent from this chart, the high electric field region extends toward the drain region with an increase of the drain current. Therefore, it is possible to prevent the resistance between the drain region and the source region of one or some of the LDMOSs from being in negative resistance region even when the ESD surge occurs by arranging so that the high electric field region reaches to the drain region when the drain current becomes equal to or greater than that at the time of ESD surge (200 A for example).
As described above, it is possible to increase the current value when the resistance between the drain region and the source region of the LDMOS is in the negative resistance region by increasing the surface concentration of the n-type region.
Further, it is possible to prevent the resistance between the drain region and the source region of the LDMOS from being in the negative resistance region more by setting the surface concentration of the n-type region so that the high electric field region reaches to the drain region when the drain current becomes equal to or greater than that at the time of ESD surge.
It is also possible to sift the inflection point 1 which also may be caused by the parasitic transistor and to prevent the resistance between the drain region and the source region of the LDMOS from being in the negative resistance region by constructing the LDMOS having the structure in which the parasitic transistor hardly turns ON.
According to the present invention, a first conductive type region is provided between a drain region and a base region on a surface layer part of a semiconductor layer. The first conductive type region is constructed so that its concentration is higher than that of the semiconductor layer and this concentration gradually increases from the semiconductor layer to the drain region.
As mentioned above, a current value at which a resistance between the source region and the drain region of a LDMOS comes into the negative resistance region can be increased and the capacity for ESD surge can be improved by disposing the first conductive type region between the drain region and the base region.
According to another aspect of the present invention, a second conductive type region is provided so as to contact to a lower part of the source region, the second conductive type region has a concentration higher than that of the base region.
The parasitic transistor hardly turns ON by providing the second conductive type region. Thereby, it is possible to prevent the resistance between the drain region and the source region of the LDMOS from coming into the negative resistance region and to improve the capacity for ESD surge.
In this case, it is preferable to dispose the second conductive type region away from the channel region.
It is preferable to form the first conductive type region before forming the drain region on a surface layer part of a semiconductor layer
It is preferable to form the first conductive type region by ion-implanting first conductive type impurity at a dosage of 1xc3x971014 cmxe2x88x922 or less. With such dosage, it is possible to make a concentration of the first conductive type region to a degree such that a sustain characteristics becomes positive reliably.
It is preferable to set the dosage of the first conductive type impurity at 2xc3x971013 cmxe2x88x922 or more. With such dosage, it is possible to make the concentration of the first conductive type region to a degree such that a depletion layer extending within the first conductive type region does not reach to the drain region.
It is preferable to set a depth of the first conductive type region at 2 to 4 pm. It is possible to prevent an interface of an oxide film (LOCOS (LOCal Oxidation of Silicon) film) from becoming unstable due to a suction (absorption) of the impurity to the oxide film by setting the depth of the first conductive type region at 2 xcexcm or more as described above. It is also possible to prevent ON resistance from increasing due to an increase of a gap between the source and the drain by setting the first conductive type region at 4 xcexcm or less.
It is preferable to carry out the step for forming the contact region by high acceleration ion implantation. In this way, a contact region is formed at a position deeper than the surface portion the semiconductor layer. Therefore, a concentration in a channel part may be suppressed low even if a concentration of the contact region is increased.